1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of improving reliability of the device by increasing a margin of the read operation for reading data stored at the memory cell.
2. Background of the Related Art
As the degree of integration in the device is increased, the area of the memory cell is reduced. At the same time, there occur several problems for the memory cell to store data.
For example, in case of a DRAM, the memory cell consists of one transistor and one capacitor. Data is stored at the memory cell by a method of charging or discharging the charge into or from the capacitor. In this case, as the size of the capacitor is reduced in order to increase the degree of integration in the degree, time when the charge stored at the capacitor is discharged is shortened. For this reason, there is a difficulty in keeping data for a long period of time.
FIG. 1 is a circuit diagram for explaining the read operation of data stored at the memory cell in a common semiconductor memory device.
Referring to FIG. 1, a memory cell array 100 includes a plurality of word lines WL0˜WLn, a plurality of bit lines BL1˜BLn and inverted bit lines BL1#˜BLn#. The gates of the memory cells in the row direction are commonly connected in the word lines WL0˜WLn. The drains of the memory cells in the column direction are commonly connected in the bit lines BL1˜BLn and inverted bit lines BL1#˜BLn#.
In the concrete, in case of a dynamic semiconductor memory device, true cells C1˜Cn connected to the bit lines BL1˜BLn and complement cells C#1˜C#n connected to the inverted bit lines BL1#˜BLn# are positioned zigzag, among the memory cell. In other words, in the memory cell array, the bit lines BL1˜BLn and inverted bit lines BL1#˜BLn# are alternately arranged and word lines WL0˜WLn are arranged in a direction orthogonal to the bit lines BL1˜BLn. Furthermore, the memory cells C1˜Cn and C#1˜C#n are not positioned in a line arrangement of a matrix shape but arranged zigzag.
Meanwhile, the bit line BL1 and inverted bit line BL1#corresponding thereto are each connected to the input terminal of the sense amplifier 120-1. This sense amplifier is provided the same number as the bit line. In this situation, if addresses A0˜Ak are inputted, a row decoder 110 decodes the inputted addresses to select one word line. A column decoder 130 selects a specific bit line (or inverted bit line). For example, if the addresses A0˜Ak are inputted and a first word line (for example WL0) and first bit line BL1 are selected, the sense amplifier 120-1 compares the reference voltage (for example Vcc/2) inputted through the inverted bit line BL#1 and charge status of the capacitor in the true cell C1 inputted through the bit line BL1 to read data stored at the true cells C1˜Cn, respectively. The read data are outputted toward the outside through a data output pin.
At this time, in case where data of ‘0’ is stored since the charge is not charged into the capacitor of the memory cell, data of ‘0’ could be stably kept since there is no any charge to be discharged. Furthermore, during the refresh or read operation, since the difference in the voltage between 0V of the bit line (for example BL1) and Vcc/2 of the inverted bit line (for example BL1#) is clearly different, error in the read operation rarely happens. However, in case where data of ‘1’ is stored since the charge is charged into the capacitor of the memory cell, data of ‘1’ could not be stably kept since the charged charge is discharged as time goes. Therefore, during the refresh or read operation, the sense amplifier (for example 120-1) must compare the difference in the voltage (a) between (a+Vcc/2) of the bit line BL1 that is lower than Vcc and (Vcc/2) of the inverted bit line BL1#. If the difference in the voltage (a) is not high, read error may occur.
Furthermore, if the degree of integration is increased and capacitance of the capacitor is thus reduced, it is required that the refresh period be shortened in order to improve a data retention characteristic. Due to this, there is a problem that current consumption and the defective rate are increased.